Over the past several years, the number of transistors in semiconductor devices has increased dramatically. Due to this increase, the time to design and manufacture semiconductor devices has also increased.
A typical semiconductor design process includes numerous steps. Initially, a schematic diagram that represents an integrated circuit is prepared. The schematic diagram provides a representation of the logical connections between logic elements that form the integrated circuit. Once the schematic diagram has been tested to verify that the circuit performs the correct functions, the schematic diagram is converted into a mask layout database that includes a series of polygons. The polygons may represent the logic elements and the logical connections from the schematic diagram. The mask layout database is then used to form a series of photomasks, also know as masks or reticles, that may be used to manufacture the different layers of the integrated circuit.
Typically, the mask layout database is created manually by a mask designer or automatically by a synthesis tool. Once the mask layout database is complete, polygons that form electrical connections in the mask layout database are compared to the logical connections from the schematic diagram. This comparison may result in connection mismatches between the schematic diagram and the mask layout database. A connection mismatch typically indicates that an electrical connection in the mask layout database does not match its corresponding logical connection in the schematic diagram.
Today, any mismatches are corrected manually by a layout designer. The layout designer first must find the correct connection and then determine how to create the correct electrical connection in the mask layout database. Typically, the layout designer is required to delete the mismatched connection in the mask layout database and locate a path through existing polygons in the mask layout database. Once an appropriate path through the mask layout database is found, the layout designer creates a new electrical connection in the mask layout database that matches the corresponding logical connection in the schematic diagram. This process of adding the new electrical connection may take several hours or days to complete. Furthermore, the layout designer may introduce design rule errors in the mask layout database when adding the new connection. Eliminating the design rule errors may additionally require several more hours or days and thus, increase the design time for the integrated circuit.